Design and implement a basic 8 Bit CPU on an FPGA board The implementation will use Verilog (or VHDL if preferred) and target a standard, widely available FPGA board like the Xilinx Coartex-A7 ensuring compatibility with Vivado. Deliverables • HDL source: well-commented modules for datapath, ALU, control unit, registers, and memory interface • Testbenches: simulation covering each instruction, plus a self-checking program counter/ALU regression • Vivado artefacts: implemented design, timing summary, resource utilisation report • Schematics: readable datapath and control diagrams (PDF or PNG) • Documentation: 4–6-page write-up describing micro-architecture choices and verification plan • Bitstream + demo program: ready-to-flash .bit file that lights LEDs or counts on a seven-segment display • Media: a few photos or a short clip showing the board running the demo